Gate driver integrated circuits (ICs) receive control signals and drive power metal-oxide-semiconductor field-effect transistors (MOSFETs). The traditional gate driver IC typically supports a wide range of positive operating voltage (i.e., −0.3 v to 40 v) for input pins. In many applications, due to the voltage difference between control ground and power ground, system-level clamping/protection devices are used for the input pins to address the reliability concern in the negative operating direction.
A new generation of gate driver ICs incorporate the capability of bi-directional operating range (i.e., −7 v to 40 v) for the input pins to eliminate the system-level clamping devices. The overall system cost is reduced with fewer devices, lower power dissipation and smaller board area. However, providing effective on-chip electro static discharge (ESD) protection is challenging for multiple bi-directional input pins with limited die area. The input pins may also have signal transient up to +/−5V per nanosecond and low leakage requirements.
It would be desirable to provide a specific effective ESD protection topology for low cost gate driver ICs with limited die area, bi-directional operation and low-leakage requirements under fast skew rate conditions.